Cypress Semiconductor /psoc63 /SCB0 /UART_RX_CTRL

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Interpret as UART_RX_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STOP_BITS 0 (PARITY)PARITY 0 (PARITY_ENABLED)PARITY_ENABLED 0 (POLARITY)POLARITY 0 (DROP_ON_PARITY_ERROR)DROP_ON_PARITY_ERROR 0 (DROP_ON_FRAME_ERROR)DROP_ON_FRAME_ERROR 0 (MP_MODE)MP_MODE 0 (LIN_MODE)LIN_MODE 0 (SKIP_START)SKIP_START 0BREAK_WIDTH

Description

UART receiver control

Fields

STOP_BITS

N/A

PARITY

N/A

PARITY_ENABLED

N/A

POLARITY

Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.

DROP_ON_PARITY_ERROR

Behaviour when a parity check fails. When ‘0’, received data is sent to the RX FIFO. When ‘1’, received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).

DROP_ON_FRAME_ERROR

Behaviour when an error is detected in a start or stop period. When ‘0’, received data is sent to the RX FIFO. When ‘1’, received data is dropped and lost.

MP_MODE

N/A

LIN_MODE

Only applicable in standard UART submode. When ‘1’, the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of ‘0’. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to ‘1’. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to ‘1’ (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.

SKIP_START

N/A

BREAK_WIDTH

N/A

Links

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